Clock signals are used for a variety of purposes in an integrated circuit device. As the complexity of digital systems increases, clocking schemes continue to become more complicated. While multiple clock generating circuits may be used to generate the multiple clock signals, clock generating circuits typically consume a large amount of chip or board space. Therefore, most systems use one clock generating circuit to generate a first clock signal called a reference clock signal, and a specialized circuit to derive other clock signals from the reference clock signal. For example, clock multipliers are used to generate one or more clock signals of higher clock frequencies from an input or reference clock signal.
An integrated circuit such as a programmable logic device (PLD) typically receives one or more external reference clock signals to generate one or more internal clock signals to operate internal digital circuits. In synchronous systems, global clock signals are used to synchronize various circuits across the integrated circuit or a board using the integrated circuit. For example, internal circuits may be clocked by a first clock signal at a first clock frequency, while input/output (I/O) circuits may be clocked by a second clock signal at a second clock frequency, where the second clock frequency may be a multiple of the first clock frequency.
Conventional clock management circuits are used in integrated circuits to perform frequency multiplication. For example, frequency multiplication is accomplished using a Phase-Locked Loop (PLL) circuit that controls the phase and frequency by adjusting an analog voltage. However, there are a number of disadvantages in using a PLL for clock multiplication. For example, analog circuits for adjusting the voltage are sensitive to the power supply and operating temperatures. PLLs are generally difficult to design, and difficult to migrate to new integrated circuit processes and power supply reductions. Finally, PLLs often have low yields, and may require external resistors and capacitors, creating an additional burden on a user of the PLL.
Similarly, delay-locked loops (DLLs) are also used as clock multipliers, and manage the propagation delay of the clock signals by using a delay line. If the delay line in the oscillator is voltage-controlled, sensitive analog circuits are also used to adjust the frequency by adjusting the voltage applied to the delay line (i.e., voltage controlled delay elements). Further, DLLs comprise a linear chain of delay elements and binary multiplexers for clock selection. Therefore, DLLs generally occupy a significant area and have large intrinsic delay. Complicated state machines are also necessary to provide the selected delay. Finally, DLLs are typically slow to lock.
Accordingly, there is a need for a circuit for and method of generating a multiplied clock signal in an integrated circuit.